The Accelerated Graphics Port (AGP) is a bus specification developed by Intel Corporation that enables high performance two-dimensional and three-dimensional graphics to be displayed quickly on ordinary personal computers. AGP uses the computer's main storage, also known as RAM (random access memory), to store graphics data. Graphics data can be accessed, transferred, manipulated, and processed for display by one or more processors in the data processing system, including special-purpose graphics processors.
Intel Corporation designs, manufactures, and sells chipsets to support advanced graphics functions in data processing systems. A chipset is a group of microchips designed to work and to be sold as a unit in performing one or more related functions.
An AGP chipset, in conjunction with a data processing system, such as a personal computer, achieves high performance at a reduced cost, compared with expensive graphics work stations, by utilizing main memory as if it were an extension of the graphics memory, so that significantly more storage space is available for graphics data, which permits a significant increase in realism and visual quality.
In addition, AGP-based systems allow advanced graphics data to be accessed directly from main memory during on-screen rendering rather than being first accessed from main memory and temporarily stored in the relatively smaller (and more expensive per storage size) local graphics memory, thus improving memory bandwidth and latency (i.e. the speed at which data is accessed from memory and transferred to where it is needed in the system) and lowering the overall system cost for equivalent performance.
System memory is typically organized into pages. Some prior AGP chipsets contain core logic to translate operating system addresses (i.e., virtual addresses) into real memory addresses through a memory-based graphics address remapping table (GART) and its associated GART driver. Each GART entry corresponds to a page in the main memory. Until recently, both the chipset and the operating system supported a common page size, for example 4 kilobytes (KB). Therefore, the GART driver performed a straight-forward 1:1 mapping between chipset pages and operating system pages that are organized as virtual pages.
However, chipsets and operating systems being developed for future release will not necessarily support the same size page. If pages are mapped by the GART driver on a 1:1 basis, large amounts of system memory space may be wasted. For example, if each operating system page is 16 KB, and each chipset page is 4 KB, then a 1:1 mapping would waste (16 KB−4 KB=12 KB) of memory for each operating system page that is mapped by the GART driver.
There is a need in the data processing art to provide methods and apparatus to map pages of disparate sizes.